1. Field of the Invention
The invention relates to a method and apparatus for high performance switching in local area communications networks such as token ring, ATM, ethernet, fast ethernet, and gigabit ethernet environments, generally known as LANs. In particular, the invention relates to a high bandwidth architecture for an optical switch or packet processor and methods that provide efficient processing of cell and packetized data by the optical switch or packet processor.
2. Description of the Related Art
As computer performance has increased in recent years, the demands on computer networks have increased. Faster computer processors and higher memory capabilities need networks having high bandwidths to enable high speed transfer of significant amounts of data. A more complete discussion of prior art networking systems can be found, for example, in SWITCHED AND FAST ETHERNET, by Breyer and Riley (Ziff-Davis, 1996), and numerous IEEE publications relating to IEEE 802 standards. Based upon the Open Systems Interconnect (OSI) 7-layer reference model, network capabilities have grown through the development of repeaters, bridges, routers, and, more recently, “switches”, which operate with various types of communication media. Thickwire, thinwire, twisted pair, and optical fiber are examples of media which has been used for computer networks.
Switches, as they relate to computer networking, are hardware-based devices which control the flow of data packets or cells based upon destination address information which is available in each packet. A properly designed and implemented switch should be capable of receiving a packet and switching the packet to an appropriate output port at what is referred to wirespeed or linespeed, which is the maximum speed capability of the particular network. Basic ethernet wirespeed is up to 10 megabits per second, and Fast Ethernet is up to 100 megabits per second. The newest ethernet is referred to as gigabit (Gbit) ethernet, and is capable of transmitting data over a network at a rate of up to 1,000 megabits per second.
With increasing speed in computer processors and higher memory capabilities, the need for high speed switches capable of 10 Gbit and 40 Gbit processing is becoming apparent. The hardware and software systems designed to meet the performance criteria for the next generation of switches have a common set of problems. These include handling data at 10 Gbit rates, adequate multicast replication and forwarding, and issues with Quality of Service (QoS) and Service Level Agreement (SLA). The latter are important in determining raw queue behavior, latency and congestion and providing traffic policing, bandwidth management and SLA support.
In the prior art, the ability to process at the 10 Gbit rate and above is limited by the software used in switching and packet processing. To overcome such limitations, dedicated hardware can be used to do the processing and have the software be concerned with the higher-level functions of the switch. Such dedicated hardware can be implemented in network components and can provide the desired functionality at the desired speeds. The difficulty with dedicated hardware solutions is that they are, by design, directed to specific processing environments and many different network components would be necessary to meet the needs of differing network setups.
Because of this, there is a need in the prior art for a network switch that is fully scalable and fully configurable to differing network environments. There is also a need for a switch can perform dedicated packet processing based on the hardware and rely minimally on higher level software and still be adaptable to varying network architectures. There is also a need in the prior art of a method of switching packets on a network switch that is highly customizable and still able to switch packet at high speeds.